Semiconductor device and fabrication method thereof

ABSTRACT

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

PRIORITY DATA

The present application is a Continuation Application of U.S. patentapplication Ser. No. 16/396,621 filed Apr. 26, 2019, issuing as U.S.Pat. No. 11,069,785, which is a Continuation Application of U.S. patentapplication Ser. No. 15/693,849, Sep. 1, 2017, now U.S. Pat. No.10,276,678, which is a Divisional Application of U.S. patent applicationSer. No. 15/142,775, filed Apr. 29, 2016, now U.S. Pat. No. 9,754,827,entitled “SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF”, each ofwhich is hereby incorporated by reference in its entirety.

BACKGROUND

In semiconductor fabrications, silicidation is used to form lowresistivity contacts between semiconductor structure such aspolycrystalline gate electrodes or source/drain region and metalcontact. However, metal residues are found after silicidation operation,and the metal residues would severely affect electrical characteristicsof semiconductor device, particularly in advanced semiconductorfabrication.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various structures are not drawn to scale. In fact, the dimensions ofthe various structures may be arbitrarily increased or reduced forclarity of discussion.

FIG. 1 is a flow chart illustrating a method for fabricatingsemiconductor device according to various aspects of the presentdisclosure.

FIGS. 2A, 2B, 2C, 2D, 2E and 2F are cross-sectional views at one ofvarious operations of manufacturing a semiconductor device according tosome embodiments of the present disclosure.

FIG. 3 is a chart illustrating an experimental result of platinumremoval effect under different conditions.

FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G and 4H are cross-sectional views at oneof various operations of manufacturing a semiconductor device accordingto some embodiments of the present disclosure.

FIGS. 5A, 5B, 5C, 5D, 5E, 5F, and 5G are cross-sectional views at one ofvarious operations of manufacturing a semiconductor device according tosome embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of elements and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper”, “on” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

As used herein, the terms such as “first”, “second” and “third” describevarious elements, components, regions, layers and/or sections, theseelements, components, regions, layers and/or sections should not belimited by these terms. These terms may be only used to distinguish oneelement, component, region, layer or section from another. The termssuch as “first”, “second”, and “third” when used herein do not imply asequence or order unless clearly indicated by the context.

As used herein, the term “semiconductor structure” refers to a structureformed of semiconductor material(s). The semiconductor material maycomprise elementary semiconductor such as silicon or germanium; acompound semiconductor such as silicon germanium, silicon carbide,gallium arsenic, gallium phosphide, indium phosphide or indium arsenide;or combinations thereof. The semiconductor structure may comprise a gateelectrode, a source region, a drain region, or any other nodes orterminals of semiconductor devices such as MOS device, logic device,memory device or other semiconductor devices. The semiconductor materialmay be doped or undoped semiconductor material. The semiconductor maycomprise polycrystalline semiconductor such as polycrystalline silicon,amorphous semiconductor such as amorphous silicon, epitaxialsemiconductor such as epitaxial silicon, or other semiconductor materialhaving other crystalline states.

As used herein, the term “metal-semiconductor compound” refers to acompound or an alloy formed of metal material(s) and semiconductormaterial(s). The metal material(s) may comprise transition metal such asnickel, platinum, cobalt, tungsten, combinations thereof, or othersuitable metals. The semiconductor material(s) may comprise elementarysemiconductor such as silicon or germanium; a compound semiconductorsuch as silicon germanium, silicon carbide, gallium arsenic, galliumphosphide, indium phosphide or indium arsenide; or combinations thereof.In some embodiments, the metal-semiconductor compound comprises metalsilicide such as nickel silicide, platinum silicide, nickel platinumsilicide or other suitable metal silicides. In some embodiments, themetal-semiconductor compound comprises metal comprises metal germanide.

In the present disclosure, a cover layer is selectively formed to coverthe metal-semiconductor compound film. The cover layer also enclosesunreacted metal residues after formation of the metal-semiconductorcompound film. The metal residue enclosed by the cover layer is easierto be removed in a wet cleaning treatment compared to the metal residuenot enclosed by the cover layer. Reduction of metal residues alleviatesvarious electrical issues such as reduction of time-dependent dielectricbreakdown (TDDB) and breakdown voltage (V_(BD)).

FIG. 1 is a flow chart illustrating a method for fabricatingsemiconductor device according to various aspects of the presentdisclosure. The method 100 begins with operation 110 in which asubstrate having a semiconductor structure formed thereon is received.The method 100 continues with operation 120 in which a metal layercomprising a first metal and a second metal is formed over the substrateand the semiconductor structure. The method 100 proceeds with operation130 in which the metal layer is thermally treated to render the metallayer react with the semiconductor structure to form ametal-semiconductor compound film on the semiconductor structure. Themethod 100 proceeds with operation 135 in which a first wet cleaningoperation is performed to preliminarily remove the unreacted metallayer. The method 100 continues with operation 140 in which a coverlayer is formed covering the metal-semiconductor compound film andexposing the substrate, wherein the cover layer encloses unreacted metalresidues. The method 100 continues with operation 150 in which a wetcleaning operation is performed to remove the unreacted metal residues.

The method 100 is merely an example, and is not intended to limit thepresent disclosure beyond what is explicitly recited in the claims.Additional operations can be provided before, during, and after themethod 100, and some operations described can be replaced, eliminated,or moved around for additional embodiments of the method.

FIGS. 2A, 2B, 2C, 2D, 2E and 2F are cross-sectional views at one ofvarious operations of manufacturing a semiconductor device according tosome embodiments of the present disclosure. As depicted in FIG. 2A andoperation 110 in FIG. 1 , a substrate 10 having semiconductor structures12 formed thereon is received. In some embodiments, the substrate 10 isa semiconductor substrate. The material of the semiconductor substrate12 may comprise elementary semiconductor such as silicon or germanium; acompound semiconductor such as silicon germanium, silicon carbide,gallium arsenic, gallium phosphide, indium phosphide or indium arsenide;or combinations thereof. The semiconductor structure 12 is formed ofsemiconductor material. In some embodiments, the semiconductor structure12 is formed of doped semiconductor material such as dopedpolycrystalline silicon. The semiconductor structure 12 may also beformed of other doped or undoped semiconductor material. For example,the semiconductor structure 12 may comprise elementary semiconductorsuch as silicon or germanium; a compound semiconductor such as silicongermanium, silicon carbide, gallium arsenic, gallium phosphide, indiumphosphide or indium arsenide; or combinations thereof. In someembodiments, the semiconductor structure 12 is configured as anelectrode or a node of a semiconductor device such as a gate electrodeor a source/drain region.

In some embodiments, a dielectric layer 14 is formed, at least partiallyenclosing the lateral surface of the semiconductor structure 12. Theupper surface of the semiconductor structure 12 is exposed by thedielectric layer 14. The dielectric layer 14 may be formed of oxide,nitride, oxynitride, or any other suitable inorganic or organicmaterials.

As depicted in FIG. 2B and operation 120 in FIG. 1 , a metal layer 16 isformed over the substrate 10 and the semiconductor structure 12. In someembodiments, the metal layer 16 is formed over the dielectric layer 14and in contact with the upper surface of the semiconductor structure 12.In some embodiments, the metal layer 16 is an alloy layer formed of aplurality of metal materials. The metal materials may include two ormore transition metal materials such as nickel (Ni), platinum (Pt),cobalt (Co), tungsten (W), titanium (Ti), combinations thereof, or othersuitable metal materials. In some alternative embodiments, the metallayer 16 is a metallic layer of a single metal material. The metalmaterial may include a transition metal material such as nickel (Ni),platinum (Pt), cobalt (Co), tungsten (W), titanium (Ti), or othersuitable metal materials.

In some exemplary embodiments, the metal layer 16 is a nickel-platinumalloy, or a nickel layer with platinum dopants, where the amount ratioof nickel to platinum may be adjusted based on different considerations.The semiconductor structure 12 is polycrystalline silicon. In someembodiments, the metal layer 16 is formed by physical vapor deposition(PVD) such as sputtering, but not limited thereto. In the presentembodiments, nickel is configured to form nickel semiconductor compound,e.g., nickel silicide. Platinum may be configured as a stabilizer fornickel silicide. In some embodiments, nickel layer with platinum dopantsis formed by physical vapor deposition (PVD) such as sputtering usingnickel-platinum target. In some alternative embodiments, the metal layer16 may be formed by other suitable deposition operations.

As depicted in FIG. 2C and operation 130 in FIG. 1 , the metal layer 16is thermally treated to render nickel react with the semiconductorstructures 12 to form metal-semiconductor compound films (nickelsilicide) 18 on the semiconductor structures respectively. During thethermal treatment, a portion of nickel elements in the metal layer 16 incontact with the semiconductor structures 12 are reacted, therebyselectively and locally forming nickel silicide on the upper surface ofthe semiconductor structures 12, respectively. On the other hands, therest portion of the metal layer 16 that is not in contact with thesemiconductor structures 12 is not reacted. In some embodiments, a rapidthermal annealing (RTA) may be performed to thermally treat the metallayer 16. Compared to the semiconductor structure (polycrystallinesilicon) 12, the metal-semiconductor compound film (nickel silicide) 18has lower resistivity, and thus the overall electrical characteristic isenhanced.

As depicted in FIG. 2D and operation 135 in FIG. 1 , the unreacted metallayer 16 is then removed from the dielectric layer 14. The dielectriclayer 14 exposes a portion e.g., upper portion, of a surface of themetal-semiconductor compound film 18. In some embodiments, the unreactedmetal layer 16 is stripped by a cleaning solution e.g., sulfuricacid-hydrogen peroxide mixture (SPM) solution, but not limited thereto.In some embodiments, the removal of the unreacted portion of the metallayer 16 is a first wet clean operation. It is appreciated thatunreacted metal residues 16P including nickel residues and platinumresidues may exist on the dielectric layer 14 after the metal layer 16is removed, which deteriorates electrical characteristics and lead todevice breakdown problems. For example, the unreacted metal residues16P, particularly platinum residues, may induce worse time dependentdielectric breakdown (TDDB) and reduce breakdown voltage (V_(BD)).

As depicted in FIG. 2E and operation 140 in FIG. 1 , a cover layer 20 isformed on the metal-semiconductor compound films 18, and encloses theportion of the surface of the metal-semiconductor compound films 18exposed by the dielectric layer 14. In some embodiments, the cover layer20 is an insulator. The cover layer 20 also encloses the unreacted metalresidues 16P. The cover layer 20 exposes the rest structures other thanthe metal-semiconductor compound films 18 such as the dielectric layer14. In some embodiments, the cover layer 20 is selectively and locallyformed on the metal-semiconductor compound films 18, and thus the coverlayer 20 is in contact with the exposed portion of the surface of themetal-semiconductor compound films 18 and encloses the unreacted metalresidues 16P, but exposes the dielectric layer 14. In some embodiments,the cover layer 20 is substantially conformal to the exposed portion ofthe surface of the metal-semiconductor compound films 18. The thicknessof the cover layer 20 may be modified so that it can enclose theunreacted metal residue 16P. In some embodiments, the thickness of thecover layer 20 is within a range of 2-30 mm, but not limited thereto.For example, the thickness of the cover layer 20 is within a range of2-5 mm, a range of 6-10 mm, a range of 11-15 mm, a range of 16-20 mm, ora range of 21-33 mm,

In some embodiments, the cover layer 20 is selectively and locallyformed on the metal-semiconductor compound films 18 by a gaseoustreatment. For example, a gas flow is introduced in reaction chamber,and the gas molecules will react with metal elements and/orsemiconductor elements of metal-semiconductor compound films 18 as wellas the unreacted metal residues 16P, thereby forming the cover layer 20.In some embodiments, the duration of the gaseous treatment is between 30seconds and 60 seconds, but not limited thereto. In some embodiments,the gaseous treatment is implemented under low temperature and low powerto alleviate adverse influence on semiconductor device. For example, theprocess temperature is between 100° C. and 1000° C., and the processpower is between 20 W and 2000 W, but not limited thereto.

In the present embodiment, an oxygen-containing gas is introduced, andoxygen will react with nickel and polycrystalline silicon ofmetal-semiconductor compound films 18 to form an oxide cover layer. Forexample, the composition of the oxide cover layer may include siliconoxide and nickel oxide. In the present embodiment, the oxygen-containinggas may include oxygen (O₂), ozone (O₃), nitrogen oxide (NO_(x)), acombination thereof, or other oxygen-containing gases.

In some alternative exemplary embodiments, a nitrogen-containing gas isintroduced, and nitrogen will react with metal element (such as nickel,platinum or other metal elements) and semiconductor element (such assilicon) of metal-semiconductor compound films 18 to form a nitridecover layer. For example, the composition of the nitride cover layer mayinclude silicon nitride, nickel nitride, platinum nitride or other metalnitrides and semiconductor nitrides. In some embodiments, thenitrogen-containing gas may include ammonia (NH₃), nitrogen (N₂),nitrogen oxide (NO_(x)), a combination thereof, or othernitrogen-containing gases.

In still some alternative exemplary embodiments, oxygen-containing gasand nitrogen-containing gas are introduced, and oxygen and nitrogen willreact with metal element (such as nickel, platinum or other metalelements) and semiconductor element (such as silicon) ofmetal-semiconductor compound films 18 to form an oxynitride cover layer.For example, the composition of the nitride cover layer may includesilicon oxynitride, nickel oxynitride, platinum oxynitride or othermetal oxynitride and semiconductor oxynitride. In some embodiments, theoxygen-containing gas may include oxygen (O₂), ozone (O₃), nitrogenoxide (NO_(x)), a combination thereof, or other oxygen-containing gases.The nitrogen-containing gas may include ammonia (NH₃), nitrogen (N₂),nitrogen oxide (NO_(x)), a combination thereof, or othernitrogen-containing gases.

In yet some alternative exemplary embodiments, a carbon-containing gasis introduced, and carbon will react with metal element (such as nickel,platinum or other metal elements) and semiconductor element (such assilicon) of metal-semiconductor compound films 18 to form a carbidecover layer. For example, the composition of the carbide cover layer mayinclude silicon carbide, nickel carbide, platinum carbide or other metalcarbides and semiconductor carbides. In some embodiments, thecarbon-containing gas may include carbon oxide (CO_(x)) or othercarbon-containing gases.

In some embodiments, at least one of an oxygen-containing gas, anitrogen-containing gas or a carbon-containing gas may be introduced soas to form a cover layer formed of oxide compound, nitride compound,oxynitride compound, carbide compound, or a combination thereof.

In some embodiments, metal atoms of the semiconductor compound film 18may diffuse into the cover layer 20 in operation 140 or successiveoperations, and thus the cover layer 20 may also contain Ni, Pt, Co, W,Ti or other metal atoms.

As depicted in FIG. 2F and operation 150 in FIG. 1 , a second wetcleaning operation is performed to remove the unreacted metal residues16P. In the second wet cleaning operation, the unreacted metal residues16P enclosed by the cover layer 20 are stripped from the upper surfaceof the dielectric layer 14. Compared to metal residue 16P not coveredwith the cover layer 20, the metal residue 16P covered with the coverlayer 20 is easier to be removed. In some embodiments, the removal ofthe unreacted metal residues 16P is a second wet clean operationsubsequent to the first wet clean operation previously discussed. Inaddition, the cover layer 20 covering the metal-semiconductor compoundfilms 18 is able to block metal atoms from exiting out of themetal-semiconductor compound films 18. Moreover, the metal residue 16Pcovered with the insulative cover layer 20 remaining on the dielectriclayer 14 is less critical to the electrical characteristics compared tothe conductive metal residue 16P not covered with the insulative coverlayer 20.

In some embodiments, the second wet cleaning operation is performedunder high temperature e.g., between 85° C. and 150° C. using sulfuricacid-hydrogen peroxide mixture (SPM) solution. SPM solution within theabove temperature range is able to effectively remove metal residues,particularly platinum residues. The concentration of the cleaningsolution may be modified. Different cleaning solutions may be selectedbased on the types of metal residues to be removed.

FIG. 3 is a chart illustrating an experimental result of platinumremoval effect under different conditions. Sample A shows that the ratioof platinum to nickel (Pt/Ni) is about 5.8% when a wet cleaningoperation using SPM solution is performed under 80° C. Sample B showsthat the Pt/Ni ratio is about 6% when a wet cleaning operation using SPMsolution is performed under 90° C. Sample C shows that the Pt/Ni ratiois reduced to about 4% when N₂O treatment is performed for about 30seconds to form a cover layer enclosing Pt residues followed by a wetcleaning operation using SPM solution. Sample D shows that the Pt/Niratio is reduced to about 2% when N₂O treatment is performed for about60 seconds to form a cover layer enclosing Pt residues followed by a wetcleaning operation using SPM solution. As shown in FIG. 3 , the metalresidue removal effect when forming a cover layer enclosing metalresidues followed by a wet cleaning operation is significantly improved.

The semiconductor device and manufacturing method of the presentdisclosure are not limited to the above-mentioned embodiments, and mayhave other different embodiments. To simplify the description and forthe convenience of comparison between each of the embodiments of thepresent disclosure, the identical components in each of the followingembodiments are marked with identical numerals. For making it easier tocompare the difference between the embodiments, the followingdescription will detail the dissimilarities among different embodimentsand the identical features will not be redundantly described.

FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G and 4H are cross-sectional views at oneof various operations of manufacturing a semiconductor device accordingto some embodiments of the present disclosure. As depicted in FIG. 4A, asubstrate 30 having a semiconductor structure formed thereon isreceived. A MOS (metal-oxide-semiconductor) device is formed over thesubstrate 30. The MOS device includes a gate electrode 32, a sourceregion 34, a drain region 36, a gate insulator 38, gate spacers 40 andisolation structures 42. The gate electrode 32 is over the substrate 30,and the gate insulator 38 is interposed between the substrate 30 and thegate electrode 32. The gate spacers 40 are formed on the lateral sidesof the gate electrode 32. The source region 34 and the drain region 36are formed in the substrate 30 at opposite sides of the gate electrode32. The isolation structures 42 such as shallow trench isolations (STIs)or field oxide (FOX) are formed in the substrate 30.

In the present embodiments, the semiconductor structure may refer to thegate electrode 32, the source region 34 and/or the drain region 36. Insome embodiments, the material of the gate electrode 32 is dopedpolycrystalline silicon, and the material of the source region 34 andthe drain region 36 is doped silicon, but not limited thereto.

As depicted in FIG. 4B, a metal layer 44 is formed over the substrate 30and the semiconductor structure. Specifically, a portion of the metallayer 44 is in contact with the semiconductor structure such as the gateelectrode 32, the source region 34 and the drain region 36.

In some embodiments, the metal layer 44 is an alloy layer formed of aplurality of metal materials. The metal materials may include two ormore transition metal materials such as nickel (Ni), platinum (Pt),cobalt (Co), tungsten (W), titanium (Ti), combinations thereof, or othersuitable metal materials. In some alternative embodiments, the metallayer 44 is a metallic layer of a single metal material. The metalmaterial may include a transition metal material such as nickel (Ni),platinum (Pt), cobalt (Co), tungsten (W), titanium (Ti), or othersuitable metal materials.

In some exemplary embodiments, the metal layer 44 is a nickel-platinumalloy, or a nickel layer with platinum dopants, where the amount ratioof nickel to platinum may be adjusted based on different considerations.The material of the gate electrode 32, the source region 34 and thedrain region 36 is doped silicon. In the present embodiments, nickel isconfigured to form nickel semiconductor compound, e.g., nickel silicide.Platinum may be configured as a stabilizer for nickel silicide. In someembodiments, nickel layer with platinum dopants is formed by physicalvapor deposition (PVD) such as sputtering using nickel-platinum target.In some alternative embodiments, the metal layer 44 may be formed byother suitable deposition operations.

As depicted in FIG. 4C, the metal layer 44 is thermally treated torender nickel react with the gate electrode 32, the source region 34 andthe drain region 36 to form metal-semiconductor compound films (nickelsilicide) 46. During the thermal treatment, a portion of nickel elementsin the metal layer 44 in contact with the gate electrode 32, the sourceregion 34 and the drain region 36 are reacted, thereby selectively andlocally forming nickel silicide on the upper surface of the gateelectrode 32, the source region 34 and the drain region 36,respectively. On the other hands, the rest portion of the metal layer 44that is not in contact with the gate electrode 32, the source region 34and the drain region 36 is not reacted. In addition, some platinumelements do not react with silicon, and remain in themetal-semiconductor compound film 46.

In some embodiments, a rapid thermal annealing (RTA) may be performed tothermally treat the metal layer 44. Compared to the gate electrode 32,the source region 34 and the drain region 36 formed of silicon, themetal-semiconductor compound film (nickel silicide) 46 has lowerresistivity, and thus the overall electrical characteristic is enhanced.

As depicted in FIG. 4D, the unreacted metal layer 44 is then removed. Insome embodiments, the unreacted metal layer 44 is stripped by a cleaningsolution e.g., sulfuric acid-hydrogen peroxide mixture (SPM) solution,but not limited thereto. It is appreciated that unreacted metal residues44P including nickel residues and platinum residues may exist on themetal-semiconductor compound film 46 and the substrate 30 after themetal layer 44 is removed, which deteriorates electrical characteristicsand lead to unexpected issues. For example, the unreacted metal residues44P, particularly platinum residues, may induce worse time dependentdielectric breakdown (TDDB) and reduce breakdown voltage (V_(BD)).

As depicted in FIG. 4E, a cover layer 48 is formed on themetal-semiconductor compound film 46. In some embodiments, the coverlayer 48 encloses the unreacted metal residues 44P on themetal-semiconductor compound film 46. The cover layer 48 exposes therest structures other than the metal-semiconductor compound films 46such as the gate spacers 40, the isolation structures 42 and thesubstrate 30, and the unreacted metal residues 44P thereon. In someembodiments, the cover layer 48 is selectively and locally formed on themetal-semiconductor compound films 46, and thus the cover layer 48 is incontact with the exposed upper surface and lateral surface of themetal-semiconductor compound films 46, and encloses the unreacted metalresidues 44P, but exposes the rest structures. The thickness of thecover layer 48 may be modified as to enclose the unreacted metal residue44P.

In some embodiments, the cover layer 48 is selectively and locallyformed on the metal-semiconductor compound films 46 by a gaseoustreatment, which is previously described.

As depicted in FIG. 4F, a wet cleaning operation is performed to removethe unreacted metal residues 44P. In the wet cleaning operation, theunreacted metal residues 44P enclosed by the cover layer 48 are strippedfrom the upper surface of the gate spacers 40, the isolation structures42 and the substrate 30. Compared to metal residue 44P not covered withthe cover layer 48, the metal residue 44P covered with the cover layer48 is easier to remove. In addition, the cover layer 48 covering themetal-semiconductor compound films 46 is able to block metal atoms fromexiting out of the metal-semiconductor compound films 46. Moreover, themetal residue 44P covered with the insulative cover layer 48 is lesscritical to the aforesaid electrical characteristics compared to theconductive metal residue 44P not covered with the cover layer 48.

In some embodiments, the wet cleaning operation is performed under hightemperature e.g., between 85° C. and 150° C. using sulfuricacid-hydrogen peroxide mixture (SPM) solution. SPM solution within theabove temperature range is able to effectively remove metal residues,particularly platinum residues. The concentration of the cleaningsolution may be modified. Different cleaning solutions may be selectedbased on the types of metal residues to be removed.

In some embodiments, an inter-layered dielectric (ILD) 50 is formed overthe substrate 30, covering the MOS device as depicted in FIG. 4G. TheILD 50 may be formed of silicon oxide, silicon nitride, or any othersuitable inorganic or organic dielectric materials. The ILD 50 ispatterned, e.g., by photolithography and etching, to form through holes50H partially exposing the upper surfaces of the cover layers 48. Thecover layers 48 may be patterned as well via the through holes 50H toform openings 48H. The through hole 50H and the opening 48H connectingto the through hole 50H partially expose a correspondingmetal-semiconductor compound film 46.

As depicted in FIG. 4H, conductive contacts 52 are formed toelectrically connected to the metal-semiconductor compound films 46respectively via the through hole 50H of the ILD 50 and the opening 48Hof the cover layer 48. The material of the conductive contact 52 mayinclude copper, aluminum or any other suitable conductive materials.

FIGS. 5A, 5B, 5C, 5D, 5E, 5F, and 5G are cross-sectional views at one ofvarious operations of manufacturing a semiconductor device according tosome embodiments of the present disclosure. In the present embodiment,an integrated circuit with a pair of embedded flash memory cell and adriving circuit is selected as an example. It will be appreciated thatalthough these cross-sectional views illustrate only a pair ofsplit-gate memory cells, in typical embodiments an integrated circuitwill include thousands, millions, billions, or even greater numbers ofsuch split gate memory cells arranged in a memory array. The finalintegrated circuit also includes peripheral circuitry that can utilizedifferent process layers (e.g., HKMG and/or replacement metal gatetechnology), such as are used in CMOS processes.

As depicted in FIG. 5A, a substrate 70 is provided. The substrate 70 hasa memory region 701 and a periphery region 702. A pair of adjacent flashmemory cells 72 is resided on the memory region 701 and a drivingcircuit 74 is resided on the periphery region 702. In some embodiments,the flash memory cell 72 is a MONOS(metal-oxide-nitride-oxide-semiconductor) cell, and the driving circuit74 is a core circuit of SRAM. The flash memory cells 72 are located overa base dielectric layer 76. In some embodiments. In some embodiments,source/drain regions (not shown) are disposed within the substrate 70.Each flash memory cell 72 includes a select gate (SG) 78, a memory gate(MG) 80, and a charge-trapping layer 82 which extends below the MG 80.In some embodiments, the material of the SGs 78 and the MGs 80 is dopedsemiconductor such as polycrystalline silicon. A contact etch-stop layer(CESL) 84 resides over the substrate 70 as well as on the outersidewalls of the SGs 78. A dielectric layer 83 is disposed over thesubstrate 70. The dielectric layer 83 surrounds the lateral surfaces ofthe SGs 78 and the MGs 80, and exposes the upper surfaces of the SGs 78and the MGs 80. In some embodiments, the dielectric layer 83 is formedof silicon oxide, silicon nitride, or any other suitable inorganic ororganic dielectric materials. Subsequently, a mask layer 86 is formedover the dielectric layer 83, and patterned to expose the flash memorycells 72. In some embodiments, the mask layer 86 includes a siliconoxide layer, but not limited thereto.

As depicted in FIG. 5B, a metal layer 88 is formed over the substrate70, covering and in contact with the SGs 78 and the MGs 80. In someembodiments, the metal layer 88 is an alloy layer formed of a pluralityof metal materials. The metal materials may include two or moretransition metal materials such as nickel (Ni), platinum (Pt), cobalt(Co), tungsten (W), titanium (Ti), or other suitable metal materials. Insome alternative embodiments, the metal layer 88 is a metallic layer ofa single metal material. The metal material may include a transitionmetal material such as nickel (Ni), platinum (Pt), cobalt (Co), tungsten(W), titanium (Ti), or other suitable metal materials.

In some exemplary embodiments, the metal layer 88 is a nickel-platinumalloy, or a nickel layer with platinum dopants, where the amount ratioof nickel to platinum may be adjusted based on different considerations.In the present embodiments, nickel is configured to form nickelsemiconductor compound, e.g., nickel silicide. Platinum may beconfigured as a stabilizer for nickel silicide. In some embodiments,nickel layer with platinum dopants is formed by physical vapordeposition (PVD) such as sputtering using nickel-platinum target. Insome alternative embodiments, the metal layer 88 may be formed by othersuitable deposition operations.

As depicted in FIG. 5C, the metal layer 88 is thermally treated torender nickel react with the SGs 78 and the MGs 80 to formmetal-semiconductor compound films (nickel silicide) 90. During thethermal treatment, a portion of nickel elements in the metal layer 88 incontact with the SGs 78 and the MGs 80 are reacted, thereby selectivelyand locally forming nickel silicide on the upper surface of the SGs 78and the MGs 80, respectively. On the other hands, the rest portion ofthe metal layer 88 that is not in contact with the SGs 78 and the MGs 80is not reacted. In some embodiments, a rapid thermal annealing (RTA) maybe performed to thermally treat the metal layer 88. Compared to the SGs78 and the MGs 80 formed of polycrystalline silicon, themetal-semiconductor compound film (nickel silicide) 90 reduces high polyresistance by providing a better low resistance contact surface for theconductive contacts to be formed subsequently and also prevents polydamage caused during contact etching. Thus, the formation of themetal-semiconductor compound film 90 increases the program/erase speedof the flash memory device by reducing the poly resistance. Duringoperation, the flash memory cells 72 may each be thought of as twotransistors in series. Within each cell, one transistor is the memorygate transistor (e.g., corresponding to MG 80), and the other is theselect gate transistor (e.g. corresponding to SG 78) which is controlledby a word line. In some embodiments, programming is performed by meansof source-side channel hot-electron injection. Poly-to-polyFowler-Nordheim (FN) electron tunneling is employed for erasing. Tochange the cell value to a “0”, a negative electrical potential isapplied to both the MG and SG transistors, such that the electronsstored in the charge-trapping layer (e.g., 82) are drained to the sourceside of the memory cell. The electrons in the cells of a chip can bereturned to normal “1” by the application of a strong positive electricfield. Because the electrons tend to remain in the charge-trapping layereven when power is disconnected from the chip, the flash memory cellsare said to be “non-volatile.”

The unreacted metal layer 88 is then removed. In some embodiments, theunreacted metal layer 88 is stripped by a cleaning solution e.g.,sulfuric acid-hydrogen peroxide mixture (SPM) solution, but not limitedthereto. It is appreciated that unreacted metal residues 88P includingnickel residues and platinum residues may exist on the substrate 70after the metal layer 88 is removed, which would deteriorate electricalcharacteristics and lead to unexpected issues. For example, theunreacted metal residues 88P, particularly platinum residues, may induceworse time dependent dielectric breakdown (TDDB) and reduce breakdownvoltage (V_(BD)).

As depicted in FIG. 5D, a cover layer 92 is formed on themetal-semiconductor compound film 90. In some embodiments, the coverlayer 92 encloses the metal-semiconductor compound film 90 and theunreacted metal residues 88P. The cover layer 92 exposes the reststructures other than the metal-semiconductor compound films 90 and theunreacted metal residues 88P. In some embodiments, the cover layer 92 isselectively and locally formed on the metal-semiconductor compound films90. Specifically, the cover layer 92 is in contact with the exposedupper surface and lateral surface of the metal-semiconductor compoundfilms 90 and encloses the unreacted metal residues 88P, but exposes therest structures. The thickness of the cover layer 92 may be modified asto be sufficient to enclose the unreacted metal residue 88P.

In some embodiments, the cover layer 92 is selectively and locallyformed on the metal-semiconductor compound films 90 by a gaseoustreatment, which is previously described.

As depicted in FIG. 5E, a wet cleaning operation is performed to removethe unreacted metal residues 88P. In the wet cleaning operation, theunreacted metal residues 88P enclosed by the cover layer 92 are strippedfrom the upper surface of the dielectric layer 83. Compared to metalresidue 88P not covered with the cover layer 92, the metal residue 88Pcovered with the cover layer 92 is easier to remove. In addition, themetal residue 88P covered with the insulative cover layer 92 remainingon the dielectric layer 83 is less critical to the aforesaid electricalcharacteristics compared to the conductive metal residue 88P not coveredwith the cover layer 92.

In some embodiments, the wet cleaning operation is performed under hightemperature e.g., between 85° C. and 150° C. using sulfuricacid-hydrogen peroxide mixture (SPM) solution. SPM solution within theabove temperature range is able to effectively remove the metal residues88P enclosed by the cover layer 92, e.g., platinum residues enclosed byoxide cover layer. The concentration of the cleaning solution may bemodified. Different cleaning solutions may be selected based on thetypes of metal residues to be removed.

As shown in FIG. 5F, an inter-layered dielectric (ILD) 94 is formed overthe substrate 70, covering the flash memory cells 72 and the drivingcircuit 74. The ILD 94 may be formed of silicon oxide, silicon nitride,or any other suitable inorganic or organic dielectric materials. The ILD94 is then patterned, e.g., by photolithography and etching, to formthrough holes 94H partially exposing the upper surfaces of the coverlayers 92. The cover layers 92 may be patterned as well via the throughholes 94H to form openings 92H. The through hole 94H and the opening 92Hconnecting to the through hole 94H partially expose a correspondingmetal-semiconductor compound film 90.

As depicted in FIG. 5G, conductive contacts 96 are formed toelectrically connected to the metal-semiconductor compound films 90respectively via the through hole 94H of the ILD 94 and the opening 92Hof the cover layer 92. The material of the conductive contact 96 mayinclude copper, aluminum or any other suitable conductive materials.

In the present disclosure, the metal-semiconductor compound film atopthe semiconductor structure is partially covered with a cover layer. Thecover layer is configured to enclose unreacted metal residues, therebymaking it easier to remove the metal residues with a wet cleaningtreatment. Accordingly, various electrical issues such as reduction oftime dependent dielectric breakdown (TDDB) and breakdown voltage(V_(BD)) are significantly alleviated.

In one exemplary aspect, a semiconductor device is provided. Thesemiconductor device comprises a semiconductor structure, a dielectriclayer, a metal-semiconductor compound film, and a cover layer. Thesemiconductor structure has an upper surface and a lateral surface. Thedielectric layer encloses the lateral surface of the semiconductorstructure and exposes the upper surface of the semiconductor structure.The metal-semiconductor compound film is on the semiconductor structure,wherein the dielectric layer exposes a portion of a surface of themetal-semiconductor compound film. The cover layer encloses the portionof the surface of the metal-semiconductor compound film exposed by thedielectric layer, and exposes the dielectric layer.

In another exemplary aspect, a semiconductor device is provided. Thesemiconductor device comprises a semiconductor substrate, a gateelectrode, a metal-semiconductor compound film, a dielectric layer, acover layer, an inter-layered dielectric (ILD), and a conductivecontact. The metal-semiconductor compound film is on the gate electrode.The dielectric layer encloses the gate electrode and exposes a portionof a surface of the metal-semiconductor compound film. The cover layeris on the portion of the surface of the metal-semiconductor compoundfilm, and exposes an upper surface of the dielectric layer. The coverlayer has an opening partially exposing the portion of the surface ofthe metal-semiconductor compound film. The ILD is over the dielectriclayer, wherein the ILD has a through hole connecting the opening of thecover layer. The conductive contact is electrically connected to themetal-semiconductor compound film via the through hole of the ILD andthe opening of the cover layer.

In yet another aspect, a method for fabricating semiconductor device isprovided. The method includes the following operations. A substratehaving a semiconductor structure formed thereon is received. A metallayer is formed over the substrate and the semiconductor structure. Themetal layer is thermally treated to render the metal layer react withthe semiconductor structure to form a metal-semiconductor compound filmon the semiconductor structure. A cover layer covering themetal-semiconductor compound film and exposing the substrate is formed,wherein the cover layer encloses unreacted metal residues. A wetcleaning operation is performed to remove the unreacted metal residues.

The foregoing outlines structures of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method for fabricating semiconductor device,comprising: receiving a substrate having a structure formed thereon;forming a layer over the substrate and the structure, wherein the layerincludes a metal; reacting a first portion of the layer with a surfaceof the structure to form a metal-semiconductor compound film; performinga first process to remove a second portion the layer; and afterperforming the first process, forming a cover layer covering themetal-semiconductor compound film, wherein the cover layer includes themetal and at least one of oxygen and nitrogen.
 2. The method of claim 1,wherein the metal is at least one of nickel or platinum.
 3. The methodof claim 1, wherein forming the cover layer on the metal-semiconductorcompound film comprises introducing an oxygen-containing gas reactingwith the metal-semiconductor compound film to form an oxide.
 4. Themethod of claim 1, wherein forming the cover layer on themetal-semiconductor compound film comprises introducing anitrogen-containing gas reacting with the metal-semiconductor compoundfilm to form a nitride.
 5. The method of claim 1, wherein forming thecover layer on the metal-semiconductor compound film comprisesintroducing a carbon-containing gas reacting with themetal-semiconductor compound film to form a carbide.
 6. The method ofclaim 1, further comprising: cleaning a surface of the cover layer. 7.The method of claim 1, wherein the removing the second portion of thelayer includes removing an unreacted metal.
 8. A method for fabricatingsemiconductor device, comprising: receiving a substrate having astructure formed thereon; forming a metal layer over the substrate andthe structure; thermally treating the metal layer to form ametal-semiconductor compound film on the structure including a firstmetal; removing an unreacted portion of the metal layer; and afterremoving the unreacted portion, introducing a gas including a firstmaterial, wherein the first material is at least one of oxygen, nitrogenor carbon, wherein the introducing the gas forms a dielectric comprisingthe first metal and the first material disposed over themetal-semiconductor compound film.
 9. The method of claim 8, wherein thethermally treating the metal layer includes an anneal.
 10. The method ofclaim 8, further comprising: applying a sulfuric acid-hydrogen peroxidemixture (SPM) solution after removing the unreacted portion.
 11. Themethod of claim 8, further comprising: forming a contact structureextending through the dielectric to interface the metal-semiconductorcompound film.
 12. The method of claim 8, wherein the receiving thesubstrate includes forming the structure including a source/drainregion.
 13. The method of claim 8, wherein the receiving the substrateincludes forming the structure including a gate electrode.
 14. Themethod of claim 8, further comprising: forming the structure and formingan additional structure, wherein the structure and the additionalstructure are one of a gate electrode and a source/drain region; andwherein the forming the metal-semiconductor compound film includesforming a portion of the metal-semiconductor compound film on theadditional structure.
 15. A method of fabricating a semiconductordevice, comprising: forming a memory cell on a first region of asubstrate, and a circuit component on a second region of the substrate;forming a mask layer over the second region of the substrate and a metallayer over the first region of the substrate; reacting the metal layerwith a first gate structure of the memory cell while the mask layer isover the second region, wherein the reacting forms a compound film onthe first gate structure; selectively forming a cover layer over thecompound film on the first gate structure; forming a dielectric layerover the cover layer and over the mask layer; and forming a conductivecontact extending through the dielectric layer and the cover layer tothe compound film.
 16. The method of claim 15, further comprising:reacting the metal layer with a first source/drain region adjacent thefirst gate structure, wherein the reacting forms a second compound filmon the first source/drain region.
 17. The method of claim 16, whereinthe forming the conductive contact includes forming a first contactinterfacing the compound film on the first gate structure and forming asecond contact interfacing the second compound film on the firstsource/drain region.
 18. The method of claim 16, wherein the selectivelyforming the cover layer includes forming at least one of metal oxide, ametal nitride, or a metal oxynitride.
 19. The method of claim 15,wherein the forming the mask layer includes forming silicon oxide. 20.The method of claim 15, further comprising: prior to forming the masklayer, depositing another dielectric layer extending from the firstregion to the second region.